A framework for customizable deep neural network hardware generation on FPGA

Please use this identifier to cite or link to this item: http://tailieuso.udn.vn/handle/TTHL_125/7433

Full metadata record

DC Field	Value	Language
dc.contributor.author	Huynh, Viet Thang	-
dc.contributor.author	Huynh, Minh Vu	-
dc.contributor.author	Ho, Phuoc Tien	-
dc.date.accessioned	2018-01-04T04:49:12Z	-
dc.date.available	2018-01-04T04:49:12Z	-
dc.date.issued	2017	-
dc.date.submitted	2017	-
dc.identifier.issn	1859-1531	-
dc.identifier.uri	http://tailieuso.udn.vn/handle/TTHL_125/7433	-
dc.description	The University of Danang, Journal of Science and Technology, No.11(120).2017, Vol.4; PP. 68 – 71.	en
dc.language.iso	en	en
dc.publisher	The University of Danang	en
dc.source	The University of Danang	en
dc.subject	Deep neural network	en
dc.subject	Pattern recognition	en
dc.subject	FPGA	en
dc.subject	Hardware implementation	en
dc.subject	Floating-point	en
dc.subject	MNIST	en
dc.title	A framework for customizable deep neural network hardware generation on FPGA	en
dc.title.alternative	Nền tảng cho thực thi mạng nơ-ron sâu tùy biến được trên FPGA	en
dc.type	Article	en
Appears in Collections:	2017

Files in This Item:

File	Description	Size	Format
AFramework.TT.pdf	Abstracts	89.72 kB	Adobe PDF	View/Open
AFramework.TV.pdf	Contents	528.24 kB	Adobe PDF	View/Open Request a copy